Title :
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS
Author :
Yamaguchi, Hitoshi ; Tamura, H. ; Doi, Yoshihito ; Tomita, Yasumoto ; Hamada, Takahiro ; Kibune, Masaya ; Ohmoto, S. ; Tateishi, Kenju ; Tyshchenko, Oleksiy ; Sheikholeslami, Ali ; Higuchi, Tatsuro ; Ogawa, Jun ; Saito, Takashi ; Ishida, Hiroto ; Gotoh, K
Author_Institution :
Fujitsu Labs., Kawasaki, Japan
Abstract :
An SSC-compliant 5 Gb/s transceiver in 65 nm CMOS is developed and tested. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase difference between the sampling clock and the signal. The phase tracking of the input signal and the data decision are performed entirely in the numerical domain.
Keywords :
CMOS integrated circuits; adaptive equalisers; analogue-digital conversion; clock and data recovery circuits; transceivers; ADC-based feedforward CDR; CMA adaptive equalizer; CMOS; SSC-compliant transceiver; bit rate 5 Gbit/s; data decision; input signal; numerical domain; phase difference; phase tracking; size 65 nm; spread-spectrum-clocking; Adaptive equalizers; Clocks; Finite impulse response filter; Frequency; Logic; Physical layer; Propagation losses; Quantization; Transceivers; Transmitters;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5434001
