Title :
Genetic algorithm accelerator GAA-II
Author :
Wakabayashi, Shinichi ; Koide, Tetsushi ; Toshine, Naoyoshi ; Yamane, Masataka ; Ueno, Hajime
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
Abstract :
We have developed a new GA hardware called GAA-I (genetic algorithm accelerator-I), in which the crossover operator to be applied to each individual was dynamically selected during the algorithm execution. GAA-I has some restrictions due to the limited chip size. In this paper, we extend the GAA-I and propose a new GA hardware, GAA-II, so that large, complex optimization problems can be solved, Furthermore, GAA-II has capability of parallel processing with other GAA-II chips. The GAA-II chip has been fabricated as a CMOS standard cell chip with 0.6 /spl mu/m technology.
Keywords :
CMOS logic circuits; cellular arrays; genetic algorithms; parallel architectures; 0.6 micron; CMOS standard cell chip; GAA-II; algorithm execution; chip size; complex optimization problems; crossover operator; genetic algorithm accelerator; parallel processing; Acceleration; Biological cells; Design engineering; Genetic algorithms; Genetic engineering; Hardware; Parallel processing; Random access memory; Robustness; Space technology;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835053
