Title :
A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS
Author :
Hossain, M. ; Carusone, Anthony Chan
Author_Institution :
Univ. of Toronto, Toronto, ON, Canada
Abstract :
The clock path in a 65 nm CMOS receiver comprises two injection-locked oscillators to frequency-multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Latency mismatch and data rates are accommodated by controlling jitter tracking up to 300 MHz. Each receiver consumes 0.92 pJ/b at 7.4 Gb/s with a jitter tolerance of 1.5UI at 200 MHz.
Keywords :
CMOS integrated circuits; injection locked oscillators; radio receivers; 65 nm CMOS receiver; bit rate 7.4 Gbit/s; clock-forwarded receiver; frequency 200 MHz; frequency 300 MHz; injection-locked oscillators; jitter tolerance; jitter tracking; latency mismatch; power 6.5 mW; Bandwidth; Circuits; Clocks; Delay; Filters; Frequency; Injection-locked oscillators; Jitter; Transceivers; Tuning;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5434007
