Title :
FPGA Frequency Domain Based GPS Coarse Acquisition Processor Using FFT
Author :
Sajabi, Cyprian ; Chen, Chien-In Henry ; Lin, David M. ; Tsui, James B Y
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH
Abstract :
In this paper we describe the use of the FFT on an FPGA to perform lock on coarse acquisition (C/A) code and carrier frequency in a global positioning system (GPS) receiver. A novel technique of sub-sampling is used in this system to obtain data block sizes that match hardware limitations. The system uses 10 ms of data to perform the lock with 6 ms of processing time and theoretically can operate on signals 20 db below the noise floor
Keywords :
Global Positioning System; fast Fourier transforms; field programmable gate arrays; receivers; 10 ms; 6 ms; carrier frequency; coarse acquisition processor; data block sizes; fast Fourier transform; field programmable gate arrays; global positioning system receiver; noise floor; sub-sampling technique; Bandwidth; Discrete Fourier transforms; Field programmable gate arrays; Frequency domain analysis; Global Positioning System; Hardware; Modulation coding; Satellite navigation systems; Signal processing; Spread spectrum communication; FPGA; GPS; coarse acquisition (C/A) code; discrete Fourier transform (DFT); fast Fourier transform (FFT); inverse fft (IFFT); signal-to-noise ratio(S/N;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE
Conference_Location :
Sorrento
Print_ISBN :
0-7803-9359-7
Electronic_ISBN :
1091-5281
DOI :
10.1109/IMTC.2006.328619
