Title :
An efficient heuristic for state encoding minimizing the BDD representations of the transition relations of finite state machines
Author :
Forth, Riccardo ; Molitor, Paul
Author_Institution :
Inst. for Comput. Sci., Halle-Wittenberg Univ., Germany
Abstract :
An efficient representation of the (smoothed) transition relation of a synchronous finite state machine (FSM) speeds up the traversal based symbolic verification and the functional simulation of the FSM. When using reduced ordered binary decision diagrams (BDDs), dynamic reordering algorithms are applied in order to keep the sizes of the BDDs tractable. However when FSMs are represented by BDDs, the state encoding can be used as an additional optimization criterion. In this paper, we present a new algorithm for state encoding of FSMs that minimizes the BDD representations of the corresponding (smoothed) transition relations. Experimental results show the approach to be very efficient.
Keywords :
binary decision diagrams; circuit optimisation; directed graphs; finite state machines; logic simulation; minimisation of switching nets; sequential circuits; BDD representation minimization; FSMs; STG graph; dynamic reordering algorithms; functional simulation; heuristic; optimization criterion; reduced ordered binary decision diagrams; sequential circuit optimization; smoothed transition relation; state encoding; subtrees; synchronous finite state machine; transition relations; traversal based symbolic verification; Automata; Binary decision diagrams; Boolean functions; Computational modeling; Computer science; Computer simulation; Data structures; Electronic mail; Encoding; Sequential circuits;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835071