Title :
Self-reforming routing for stochastic search in VLSI interconnection layout
Author :
Kubo, Yukiko ; Takashima, Yasuhiro ; Nakatake, Shigetoshi ; Kajitani, Yoji
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
Given a route which connects terminals on a one-layer routing area (Steiner tree), flip is a procedure that makes a current route change its configuration within its peripheral domain. A flip reforms a route by replacing one of its edges with a minimal detour. A route can flip one nearby obstacle. If the obstacle is another route, a more organized operation, called the dual flip, is applied to a pair of routes. The idea is enhanced to 2-layer hv-routing. The performance of flip and dual flip was tested in simulated annealing which reforms a route or a set of routes with respect to the evaluation function of multiple objectives. Some unique and satisfiable results were observed.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; network routing; search problems; simulated annealing; trees (mathematics); Steiner tree; VLSI interconnection layout; dual flip; flip; minimal detour; multiple objective evaluation function; one-layer routing area; self-reforming routing; simulated annealing; stochastic search; Automation; Concrete; Crosstalk; Delay; Information science; Joining processes; Routing; Simulated annealing; Stochastic processes; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835076