Dual Time Delay Digital Tanlock Loop with improved performance

A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction of phase noise or jitter which makes it well suited to operate in noisy environment. The performance of the D-TDTL system was demonstrated using frequency shift keying (FSK) input signal with AWGN noise.