A software-implemented fault-tolerant technique for microprocessor controllers

A fault-tolerant technique implemented transparently on application software is presented to detect invalid branches. A preliminary assessment is made using experiments that emulate and physically inject faults into example programs on 8-b Motorola 68(7)05, 16-b Motorola 68000, and 32-b Intel 80386 microprocessor systems. Preliminary results are encouraging and suggest that further studies of larger and more complex systems will be necessary to determine fully the benefit of the technique. The method is designed to be incorporated into a strategic selection of capability checks that collectively cover many fault classes leading to high and cost-effective reliability