A hybrid approach for core-based system-level power modeling

Reducing power consumption has become a key goal for system-on-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction methods tend to have greater impact at higher abstraction levels. Unfortunately, current approaches to power estimation which concentrate on register-transfer-level models or lower are quite slow. Higher-level approaches, while faster, may suffer from inaccuracy. However the advent of cores enables a hybrid approach, described in this paper yielding both fast and accurate estimates from high-level models. In particular, we use power estimation data obtained from the gate-level for a core´s representative input stimuli data (instructions), and we propagate this data to a higher (object-oriented) system-level model, which is parameterizable and executable. Depending on the kind of cores, various parameterizable equation or look-up table based techniques are used, resulting in self-analyzing core models. We have applied our technique to several cores of a digital camera SOC and have achieved simulation speedups of over 1000 with accuracies suitable for making reliable power-related system-level design decisions. Although we focus on power estimation, our approach can be used for estimating other metrics as well, such as performance and size.