Synthesis of low power folded programmable coefficient FIR digital filters

A novel low-power synthesis technique is presented for the design of folded or time-multiplexed programmable-coefficient FIR filters where storage area is traded-off for lowering power consumption. A systematic technique is developed for low power mapping of FIR filters to architectures with arbitrary number of multipliers and adders. Power consumed in multipliers is reduced by reducing switching activity at both the data-in as well as the coefficient input. Common input operands can be exposed unfolding, which, however leads to a memory Increase. Simulation are obtained for folding 65 and 129 tap bandpass FIR filters. The average power consumed in a multiplier for a fixed number of hardware multipliers with varying unfolding factors is compared. It is observed that most of the gains due to unfolding are obtained for relatively small unfolding factors and therefore for relatively small memory area overhead. Depending on the unfolding factor employed the average power consumed in a multiplier is seen to reduce anywhere from 54.75% to 81.73% when transpose FIR filters are synthesized as opposed to synthesizing direct-form FIR filters with no unfolding.