A 40nm 16-core 128-thread CMT SPARC SoC processor

Author

Shin, Jinuk Luke ; Tam, Kimo ; Huang, Dijiang ; Petrick, Bruce ; Pham, Hieu ; Changku Hwang ; Hongping Li ; Smith, A. ; Johnson, Tyler ; Schumacher, Frank ; Greenhill, D. ; Leon, Ana Sonia ; Strong, A.

Author_Institution

Sun Microsyst., Santa Clara, CA, USA

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

98

Lastpage

99

Abstract

A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to maximize throughput. The 6 MB L2 cache of 461GB/S and the 308-pin SerDes I/O of 2.4 Tb/s support the required bandwidth. Six clock and four voltage domains, as well as power management and circuit techniques, optimize performance, power, variability and yield trade-offs across the 377 mm² die.

Keywords

system-on-chip; 16-Core 128-Thread CMT SPARC SoC Processor; 308-pin SerDes I/O; 4-way glueless system; byte rate 2.4 TByte/s; byte rate 461 GByte/s; memory size 6 MByte; performance optimization; power management; power optimization; size 40 nm; variability optimization; yield trade off optimization; Bandwidth; Clocks; Decision feedback equalizers; Integrated circuit interconnections; Latches; Logic testing; Phase locked loops; Random access memory; Voltage; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5434030

Filename

5434030