Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

This paper presents a method for hardware-software cosynthesis with run-time incrementally reconfigurable FPGAs. To reduce the run-time overhead of reconfiguring FPGAs, we present a concept called early partial reconfiguration (EPR) which minimizes the overhead by performing reconfiguration for an operation (or a task in our terms) mapped to an FPGA as early as possible so that the operation is ready to start when its execution is requested. For further reduction of the overhead, we integrate the incremental reconfiguration (IR) of FPGAs with the EPR concept. We present an ILP formulation and an efficient heuristic algorithm based on the EPR and IR concepts. Experiments on embedded system examples and synthetic examples show the efficiency of the proposed method.