DocumentCode
1889613
Title
A 45nm 37.3GOPS/W heterogeneous multi-core SoC
Author
Yuyama, Y. ; Ito, Minora ; Kiyoshige, Y. ; Nitta, Yoshinori ; Matsui, Soya ; Nishii, O. ; Hasegawa, Akio ; Ishikawa, Masatoshi ; Yamada, Tomoaki ; Miyakoshi, Junji ; Terada, Kenji ; Nojiri, T. ; Satoh, Masatoshi ; Mizuno, Hidenori ; Uchiyama, Kenji ; Wada
Author_Institution
Renesas Technol., Kodaira, Japan
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
100
Lastpage
101
Abstract
A 648 MHz 153.8 mm2 45 nm CMOS SoC integrates eight general-purpose CPUs, four dynamically reconfigurable processors, two 1024-way matrix-processors, peripherals and interfaces. Using core enhancement, DDR3-I/F improvement and clock buffer deactivation, this SoC achieves 37.3 GOPS/W at 1.15 V.
Keywords
CMOS integrated circuits; microprocessor chips; system-on-chip; CMOS SoC; clock buffer deactivation; dynamically reconfigurable processor; general purpose CPU; heterogeneous multi-core SoC; matrix processor; size 45 nm; voltage 1.15 V; Arithmetic; Central Processing Unit; Circuits; Clocks; Delay; Energy consumption; Image motion analysis; Iron; Optical buffering; Spatial databases;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5434031
Filename
5434031
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