DocumentCode
1889623
Title
Session 5 overview: Processors
Author
Rusu, Stefan ; Leon, Sonia
Author_Institution
Intel, Santa Clara, CA, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
94
Lastpage
95
Abstract
Processors have long been the leading edge of integration and process technology and this year´s papers emphatically demonstrate that this is still the case. This year´s crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore´s law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.
Keywords
Bandwidth; Crops; Embedded computing; Energy management; Innovation management; Network servers; Paper technology; Random access memory; Throughput; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5434032
Filename
5434032
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