DocumentCode :
1889801
Title :
Data transmission over a bus with peak-limited transition activity
Author :
Sundararajan, V. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
2000
fDate :
9-9 June 2000
Firstpage :
221
Lastpage :
224
Abstract :
Transitions on high capacitance buses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in the literature to encode the input signal in order to reduce the number of transitions. Reducing number of transitions comes in exchange for redundancy in data transferred over the buses. For a given amount of redundancy there exists a lower bound on the average number of transitions. In recent times noise and reliability problems have brought the peak/instantaneous power consumed in VLSI systems to prominence. There has been limited study done on reducing the number of instantaneous transitions and hence the peak power consumed in buses. In this paper, we model a bus with a limit on the maximum instantaneous transition activity as a constrained channel and derive an upper bound on the data-rate obtainable using the capacity of the underlying channel. We then demonstrate that some existing bus encoding schemes are near-optimal with respect to the derived bounds thus, perhaps, obviating the need to search for newer more complicated coding schemes. Also considered is a bus with a constraint on number of transitions in a fixed number of (k) bus transmissions. The capacity of such a bus is derived in the same manner as a bus with a constraint on maximum instantaneous transition activity.
Keywords :
VLSI; capacitance; digital integrated circuits; encoding; graph theory; low-power electronics; redundancy; VLSI systems; constrained channel; data transmission; high capacitance buses; instantaneous transition activity; peak-limited transition activity; power dissipation; redundancy; Capacitance; Data communication; Energy consumption; Power dissipation; Power system modeling; Power system reliability; Read-write memory; Redundancy; Upper bound; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
Type :
conf
DOI :
10.1109/ASPDAC.2000.835100
Filename :
835100
Link To Document :
بازگشت