Power analysis and implementation of a low-power 300-MHz 8-b/spl times/8-b pipelined multiplier

Author

Jinn-Shyan Wang ; Po-Hui Yang

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan

fYear

2000

fDate

9-9 June 2000

Firstpage

225

Lastpage

228

Abstract

This paper analyzes the power consumption of an array pipelined multiplier. To precisely realize a low power pipelined multiplier, the analytical model for a clocking system is presented. Simulation results show that the storage element is the key-component in a high performance pipelined multiplier macro. Compared with the conventional DFF and latch, the new low power DFF as PTTFF achieves a total power reduction ranging between 34 and 62 percent in a pipelined multiplier macro.

Keywords

CMOS logic circuits; flip-flops; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; logic design; low-power electronics; multiplying circuits; pipeline arithmetic; timing; 0.6 micron; 300 MHz; 8 bit; analytical model; array pipelined multiplier; clocking system; low power D-type flip-flop; low-power pipelined multiplier; multiplier macro; power analysis; power consumption; power reduction; storage element; Analytical models; Clocks; Digital signal processing chips; Driver circuits; Energy consumption; Logic arrays; Parasitic capacitance; Very large scale integration; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835101

Filename

835101