A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS

Author

Hyunwon Moon ; Sangyoub Lee ; Seung-Chan Heo ; Hwayeal Yu ; Jinhyunck Yu ; Ji-Soo Chang ; Seung-Il Choi ; Byeong-Ha Park

Author_Institution

Samsung Electron., Yongin, South Korea

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

68

Lastpage

69

Abstract

A 2.5 mm² GPS radio chip with a robust interference rejection performance working in the L1 band at 1575.42 MHz is implemented in a 65 nm CMOS process. The receiver with internal LNA shows 2.3 dB NF, 30 dB IRR, and -15 dBm blocker IP_1dB at 1710 MHz. Power consumption of 23 mW from a single 1.8 V supply is achieved by using a switched-mode power supply (SMPS).

Keywords

CMOS integrated circuits; Global Positioning System; low noise amplifiers; radio receivers; radiofrequency interference; switched mode power supplies; 65 nm CMOS process; frequency 1575.2 MHz; frequency 1710 MHz; fully integrated GPS receiver; gain 15 dB; gain 2.3 dB; gain 30 dB; power 23 mW; robust interferer rejection; switched-mode power supply; voltage 1.8 V; Calibration; Filters; Frequency synthesizers; Global Positioning System; Linearity; Receivers; Robustness; Signal resolution; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5434047

Filename

5434047