A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS

A 2.5 mm² GPS radio chip with a robust interference rejection performance working in the L1 band at 1575.42 MHz is implemented in a 65 nm CMOS process. The receiver with internal LNA shows 2.3 dB NF, 30 dB IRR, and -15 dBm blocker IP_1dB at 1710 MHz. Power consumption of 23 mW from a single 1.8 V supply is achieved by using a switched-mode power supply (SMPS).