Title :
Power reduction by simultaneous voltage scaling and gate sizing
Author :
Chen, Chunhong ; Sarrafzadeh, Majid
Author_Institution :
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Abstract :
This paper proposes to use voltage-scaling (VS) and gate-sizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the Maximum-Weighted-Independent-Set problem. We describe the clock distribution of the circuit, completeness of gate library and discreteness of supply voltage, and discuss their effects on power optimization. Experimental results show that the average power reduction ranges from 23.3% to 56.9% over all tested circuits.
Keywords :
CMOS digital integrated circuits; circuit CAD; circuit optimisation; high level synthesis; integrated circuit design; low-power electronics; timing; CMOS circuits; clock distribution; gate-sizing; maximum-weighted-independent-set problem; power consumption; power optimization; power reduction; simultaneous voltage scaling/gate sizing; timing constraints; voltage-scaling; CMOS logic circuits; Capacitance; Circuit synthesis; Circuit testing; Delay effects; Dynamic voltage scaling; Energy consumption; Libraries; Power dissipation; Timing;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835120
