Title :
Low-power design of sequential circuits using a quasi-synchronous derived clock
Author :
Xunwei Wu ; Jian Wei ; Pedram, Massoud
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., China
Abstract :
This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master clock and using it to isolate the flip flops in the circuit from the unwanted triggering action of the master clock. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.
Keywords :
CMOS logic circuits; VLSI; flip-flops; integrated circuit design; logic design; low-power electronics; sequential circuits; timing; circuit design technique; decimal counter; flip flops; low-power design; power dissipation; power saving; quasi-synchronous derived clock; sequential circuits; Clocks; Combinational circuits; Delay effects; Flip-flops; Hazards; Latches; Logic design; Power dissipation; Propagation delay; Sequential circuits;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835122
