Title :
Timing closure: the solution and its problems
Author :
Otten, Ralph H J M
Author_Institution :
Eindhoven Univ. of Technol., Netherlands
Abstract :
In this paper we summarize the derivation of the size equations, the key to timing closure, which is the dimensioning of a logic network such that timing constraints are satisfied. Next we present a number of problems when applying these equations in practice. The main ones are network generation, discrete libraries, size constraints, and resistive interconnect.
Keywords :
circuit CAD; circuit layout CAD; integrated circuit layout; integrated logic circuits; logic CAD; timing; discrete libraries; floorplanning; logic network dimensioning; logic synthesis; network generation; resistive interconnect; size constraints; size equations; timing closure; timing constraints; Delay; Ear; Equations; Libraries; Logic gates; Network synthesis; Parasitic capacitance; Sufficient conditions; Timing; Topology;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835124
