A 4-GHz CMOS dual-modulus prescaler with enhanced input sensitivity over extended operation range

This paper presents an integrated 4 GHz divide-by-16/17 dual-modulus prescaler (DMP) with enhanced input sensitivity over extended operation range for ultra-wide band (UWB) transceiver. By modeling the n-stage differential CML D flip-flop ring oscillator based injection-locked frequency divider (ILFD), tradeoffs associated with input sensitivity, locking range and the sizes of the transistors have been derived. Fabricated with SMIC 0.18 mum CMOS technology, the proposed prescaler features enhanced input sensitivity of less than -3 dBm over operation range from 3 GHz to 4.6 GHz. The ratio of the operation range (1.6 GHz) to the maximum operation frequency (4.6 GHz) achieves 35%. The measured phase noise is -110 dBc/Hz at 10 kHz. The core area required is only 0.05mm². The circuit draws 5.4 mA from a single 1.8 V supply.