Performance driven multiway partitioning

Under the interconnect-centric design paradigm, partitioning is seen as the crucial step that defines the interconnect. To meet the performance requirement of today\´s complex design, performance driven partitioners must consider the amount of interconnect induced by partitioning as well as its impact on performance. In this paper, we provide new performance driven formulation for cell move based top-down multiway partitioning algorithms with consideration of the local and global interconnect delay. In our "constrained acyclic partitioning" formulation, cell moves are restricted to maintain acyclicity in partitioning solution to prevent cyclic dependency among cells in different partitions. In our "relaxed acyclic partitioning" formulation, acyclic constraints are relaxed to give partitioners capability of minimizing cutsize and delay. Our new acyclic constraint based performance driven multiway partitioning algorithm FLARE obtains (i) 4% to 13% better delay compared to the state-of-the-art cutsize minimization based hMetis at almost no increase in cutsize, and (ii) 84% better cutsize compared to the state-of-the-art delay minimization based PRIME at an expense of 16% increase in delay.