Title :
Hierarchical computation of 3D interconnect capacitance using direct boundary element method
Author :
Gu, Jiangchun ; Wang, Zeyi ; Hong, Xianlong
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
The idea of Appel´s hierarchical algorithm handling the many-body problem is implemented in the direct boundary element method (BEM) for computation of 3D VLSI parasitic capacitance. Both the electric potential and normal electric field intensity on the boundary are involved, so it can be much easier to handle problems with multiple dielectrics and finite dielectric structure than the indirect BEM. Three kinds of boundaries (forced boundary, natural boundary and dielectric interface) are treated. Two integral kernels with different singularity (1/r, 1/r/sup 3/) are involved while computing the interaction between the boundary elements. These features make it significantly distinct from the hierarchical algorithm based on the indirect BEM, which only handles single dielectric, one integral kernel and one forced boundary. The coefficient matrix is generated and stored hierarchically in this paper. As a result, computation cost of the matrix is reduced, and the matrix-vector multiplication in the GMRES iteration is accelerated, so computation speed is improved significantly.
Keywords :
VLSI; boundary-elements methods; capacitance; circuit CAD; integrated circuit design; integrated circuit interconnections; matrix multiplication; 3D VLSI parasitic capacitance; 3D interconnect capacitance; Appel´s hierarchical algorithm; coefficient matrix; computation cost; dielectric interface; direct boundary element method; electric potential; finite dielectric structure; forced boundary; hierarchical computation; integral kernels; many-body problem; matrix-vector multiplication; multiple dielectrics; natural boundary; normal electric field intensity; singularity; Acceleration; Boundary element methods; Dielectrics; Electric potential; Finite difference methods; Integral equations; Integrated circuit interconnections; Kernel; Parasitic capacitance; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835141