An analytic calculation method for delay time of RC-class interconnects

This paper presents an analytic 3rd order calculation method, without simulations, for delay time of RC-class circuits, which can be conveniently used to model on-chip interconnects. While the proposed method requires comparable evaluation time to the previous 2nd order calculation method, it ensures more accurate results than those of 2nd order method. The proposed analytic delay calculation method guarantees allowable error tolerance when compared to the results obtained from the AWE technique or HSPICE and has better performance in evaluation time as well as numerical stability. The first algorithm of the proposed method requires 7 moments for the 3rd order approximation and yields accurate delay time approximation. The second algorithm requires 5 moments for the 3rd order approximation and results in shorter evaluation time, the accuracy of which may be less than the first algorithm.