DocumentCode
1891085
Title
Retargetable estimation scheme for DSP architecture selection
Author
Ghazal, Naji ; Newton, Richard ; Rabaey, Jan
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
2000
fDate
9-9 June 2000
Firstpage
485
Lastpage
489
Abstract
Given the recent wave of innovation and diversification in digital signal processor (DSP) architecture, the need for quickly evaluating the true potential of considered architectural choices for a given application has been rising. We propose a new scheme, called retargetable estimation, that involves analysis of a high-level description of a DSP application, with aggressive optimization search, to provide a performance estimate of its optimal implementation on the architectures considered. With this scheme, we present a new parameterized architecture model that allows quick retargeting to a wide range of architectural choices, and that emphasizes capturing an architecture´s salient optimizing features. We show that for a set of DSP benchmarks and two full applications, hand-optimized performance can be predicted reliably. We applied this scheme to two different processors.
Keywords
circuit optimisation; digital signal processing chips; high level synthesis; reconfigurable architectures; DSP architecture selection; aggressive optimization search; hand-optimized performance; high-level description; parameterized architecture model; performance estimate; retargetable estimation scheme; Application software; Application specific processors; Computer architecture; Design optimization; Digital signal processing; Digital signal processors; Embedded system; Optimizing compilers; Performance analysis; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location
Yokohama, Japan
Print_ISBN
0-7803-5973-9
Type
conf
DOI
10.1109/ASPDAC.2000.835148
Filename
835148
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