Title :
Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process
Author :
Rajagopal, Karthik
Author_Institution :
Texas Instrum. India Pvt. Ltd., Bangalore, India
Abstract :
Integration of legacy interfaces demand need for 3.3V I/Os in modern day SOCs. Low cost solutions exists by build 3.3V I/Os using specially biased 1.8V transistors imposing a serious limitation of trade-off between power, performance and reliability. This paper presents an I/O built using a dynamically biased differential amplifier based pre-driver circuit, with which excellent performance has been achieved up to 200MHz along with up to 30X reduction in power without compromise to reliability.
Keywords :
CMOS analogue integrated circuits; buffer circuits; differential amplifiers; driver circuits; low-power electronics; system-on-chip; I/O built; SOC; biased transistors; dynamically biased differential amplifier based pre-driver circuit; dynamically biased low power high performance output buffer; excellent performance; legacy interfaces; low cost solutions; single well bulk CMOS oxide process; size 45 nm; voltage 1.8 V; voltage 3.3 V; Differential amplifiers; Generators; Integrated circuit reliability; Logic gates; Steady-state; Transistors; High Voltage I/O; High speed I/O; Jitter; Low Power;
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-1034-5
DOI :
10.1109/ISQED.2012.6187489
