Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application

Author

Tsukamoto, Yasumasa ; Yabuuchi, Makoto ; Fujiwara, Hidehiro ; Nii, Koji ; Shin, Changhwan ; Liu, Tsu-Jae King

Author_Institution

Renesas Electron. Corp., Tokyo, Japan

fYear

2012

fDate

19-21 March 2012

Firstpage

270

Lastpage

274

Abstract

Quasi-Planar Tri-gate (QPT) Bulk MOSFETs are fabricated simply by slightly recessing the shallow trench isolation (STI) oxide prior to gate-stack formation. In this cost-effective manner, 7% higher performance with lower leakage current in QPT bulk devices (vs. planar bulk devices) is achieved. QPT-based single-port SRAM characteristics can be improved by employing circuit design techniques (i.e., read- and write-assist circuitry) to compensate for unequal improvements in n-channel vs. p-channel QPT devices, to improve cell yield.

Keywords

CMOS memory circuits; MOSFET; SRAM chips; integrated circuit design; isolation technology; QPT bulk CMOS technology; QPT bulk MOSFET; STI oxide; circuit design technique; gate-stack formation; leakage current; n-channel QPT device; p-channel QPT device; quasiplanar trigate bulk CMOS technology; quasiplanar trigate bulk MOSFET fabrication; shallow trench isolation oxide; single-port SRAM application; Arrays; CMOS integrated circuits; Implants; Leakage current; Logic gates; MOSFETs; Random access memory; Local Variation; Minimum Operating Voltage (Vmin); Quasi-Planar Tri-Gate Bulk MOSFET; Single-Port SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ISQED), 2012 13th International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1948-3287

Print_ISBN

978-1-4673-1034-5

Type

conf

DOI

10.1109/ISQED.2012.6187505

Filename

6187505