DocumentCode
1891586
Title
Exploring the constraints in formal verification of communication and computing systems
Author
Bogunovic, Nikola
Author_Institution
Fac. of Electr. Eng. & Comput., Zagreb Univ., Croatia
fYear
2002
fDate
2002
Firstpage
173
Lastpage
177
Abstract
The high cost of correcting errors in digital design and communication protocols of e-economy systems calls for creative formal verification methods. Unlike testing and simulation, formal verification methods cover the entire system state space and all possible combination of inputs. There are two common approaches to the problem of formal verification: theorem proving and model checking. Since the deductive approach in theorem proving has many noted shortcomings the focus of the paper is on the model checking techniques. The paper explores the constraints of the application of the verification process, finds the most difficult steps in terms of space and time complexity and proposes the necessary operations to strengthen the methodology and expand it to real-world sized examples. The state explosion problem is tackled by applying binary decision diagrams (BDD) diagrams that can efficiently represent relations (functions) and sets. Finally, the paper suggests some general research directions that are likely to lead to technological advances.
Keywords
binary decision diagrams; computational complexity; electronic commerce; error correction; formal verification; protocols; theorem proving; BDD diagrams; binary decision diagrams; cache size; communication protocols; communication systems; computing systems; design faults; digital design; dynamic variable ordering; e-economy systems; error correction; feasibility analysis; formal verification; model checking; rational product computation; recursive algorithms; software; space complexity; state explosion problem; state transition systems; system state space; theorem; theorem proving; time complexity; Boolean functions; Computational modeling; Costs; Data structures; Error correction; Explosions; Formal verification; Protocols; State-space methods; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean
Print_ISBN
0-7803-7527-0
Type
conf
DOI
10.1109/MELECON.2002.1014553
Filename
1014553
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