A 12b 50 MHz 3.3 V CMOS acquisition time minimized A/D converter

Author

Young-Deuk Jeon ; Byeong-Lyeol Jeon ; Seung-Chul Lee ; Sang-Min Yoo ; Seung-Hoon Lee

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

2000

fDate

25-28 Jan. 2000

Firstpage

613

Lastpage

616

Abstract

A 126 50 MHz CMOS analog-to-digital converter (ADC) based on a pipelined architecture was designed to demonstrate acquisition time minimization techniques for high-speed two-stage amplifiers. The proposed techniques reduce overshoots and undershoots of amplifier outputs and acquisition time by controlling the bias currents of amplifiers. The prototype ADC was fabricated in a 0.35 um double-poly triple-metal n-well CMOS technology. The measured signal-to-noise-and-distortion ratio is improved by more than 5 dB using the proposed techniques at a 50 MHz clock. The ADC power consumption is 200 mW at 3.3 V and 50 MHz.

Keywords

CMOS integrated circuits; analogue-digital conversion; minimisation; pipeline processing; 0.35 micron; 12 bit; 200 mW; 3.3 V; 50 MHz; CMOS A/D converter; CMOS ADC; acquisition time minimized ADC; bias currents control; double-poly triple-metal process; high-speed two-stage amplifiers; n-well CMOS technology; pipelined architecture; Analog-digital conversion; Bandwidth; CMOS technology; Capacitors; Design engineering; Electronic mail; Electronics industry; Industrial electronics; Minimization; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835173

Filename

835173