DocumentCode
1891765
Title
A benchmark suite for substrate analysis
Author
Charbon, Edoardo ; Silveira, Luis Miguel ; Milozzi, P.
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
fYear
2000
fDate
9-9 June 2000
Firstpage
617
Lastpage
621
Abstract
The paper proposes an initial benchmark set, suitable for substrate analysis and test. The aim is to help accurately represent electrical noise injected into and picked up from substrate in a variety of high performance circuits. Creating an accurate image of such noise is becoming a critical requirement with the expansion of real plug-and-play style designs. Several important methods for the analysis of substrate parasitic coupling are reviewed in light of the effect substrate noise has on the performance of analog and digital ICs over a wide frequency spectrum. The requirements and formats for each benchmark are described in full detail to allow possible algorithmic as well as signal integrity tests.
Keywords
analogue integrated circuits; digital integrated circuits; doping profiles; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; integrated circuit testing; monolithic integrated circuits; substrates; algorithmic tests; analog ICs; benchmark suite; digital ICs; doping profile modelling; electrical noise; high performance circuits; signal integrity tests; substrate analysis; substrate noise; substrate parasitic coupling; Benchmark testing; Circuit noise; Circuit testing; Clocks; Coupling circuits; Crosstalk; Integrated circuit interconnections; Optical coupling; Performance analysis; Rails;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location
Yokohama, Japan
Print_ISBN
0-7803-5973-9
Type
conf
DOI
10.1109/ASPDAC.2000.835174
Filename
835174
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