Title :
The combined effect of process variations and power supply noise on clock skew and jitter
Author :
Xu, Hu ; Pavlidis, Vasilis F. ; Burleson, Wayne ; Micheli, Giovanni De
Author_Institution :
Integrated Syst. Lab., EPFL, Lausanne, Switzerland
Abstract :
In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.
Keywords :
VLSI; clock distribution networks; clocks; integrated circuit noise; jitter; VLSI circuit; buffer insertion strategy; clock buffer; clock distribution network; clock jitter; clock skew; dynamic voltage scaling; power supply noise; process variation; recombinant tree; skitter; slew rate; statistical model; Accuracy; Clocks; Delay; Jitter; Monte Carlo methods; Noise; Power supplies; Clock distribution network; clock jitter; clock skew; power supply noise; process variations; skitter;
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-1034-5
DOI :
10.1109/ISQED.2012.6187512
