Title :
Direct digital frequency synthesizer with designable stepsize
Author_Institution :
RF Commun. Consulting, Santa Clara, CA, USA
Abstract :
The Variable Resolution (VR) technique for direct digital frequency synthesis (DDFS) is introduced. By manipulating the number of phase states available to the DDFS accumulator, it is shown that the frequency resolution can be designed to desired values while keeping binary arithmetic circuit structures. Examples focus on realizing exact decimal resolution and prime rational fractions thereof, such as 1/3. Measurements not only validate this design approach, but also show worst case output spurious signal magnitudes below -73 dBc from initial implementations.
Keywords :
direct digital synthesis; DDFS accumulator; direct digital frequency synthesizer; frequency resolution; variable resolution technique; Adders; Arithmetic; Circuit synthesis; Clocks; Frequency measurement; Frequency synthesizers; Radio frequency; Signal resolution; Tuning; Virtual reality; frequency synthesizers; phase control;
Conference_Titel :
Radio and Wireless Symposium (RWS), 2010 IEEE
Conference_Location :
New Orleans, LA
Print_ISBN :
978-1-4244-4725-1
Electronic_ISBN :
978-1-4244-4726-8
DOI :
10.1109/RWS.2010.5434125
