• DocumentCode
    1891943
  • Title

    Improved algorithms for hypergraph bipartitioning

  • Author

    Caldwell, Andrew E. ; Kahng, Andrew B. ; Markov, Igor L.

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • fYear
    2000
  • fDate
    9-9 June 2000
  • Firstpage
    661
  • Lastpage
    666
  • Abstract
    Multilevel Fiduccia-Mattheyses (MLFM) hypergraph partitioning is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis, has since 1997 proved itself substantially superior in both runtime and solution quality to even very recent work. In this work, we present two sets of results: (i) new techniques for flat FM-based hypergraph partitioning (which is the core of multilevel implementations), and (ii) a new multilevel implementation that offers leading-edge performance. Our new techniques for flat partitioning confirm the conjecture that specialized partitioning heuristics may be able to actively exploit fixed nodes in partitioning instances arising in the driving top-down placement context. Our FM variant is competitive with traditional FM on instances without terminals and considerably superior on instances with fixed nodes (i.e., arising during top-down placement). Our multilevel FM variant avoids several complex heuristics and non-trivial tunings that often lead to complex implementations; it achieves trade-offs between solution quality and run time that are comparable or better than those achieved by hMetis-1.5.3. We attempt to provide algorithm descriptions that are as detailed and unambiguous as possible, to allow replicability and speed improvements in future research.
  • Keywords
    VLSI; circuit layout CAD; directed graphs; iterative methods; logic partitioning; VLSI CAD physical design; balance constraints; driving top-down placement; fixed nodes; flat hypergraph partitioning; hypergraph bipartitioning; improved algorithms; iterative algorithm; multilevel Fiduccia-Mattheyses partitioning; multilevel implementation; specialized partitioning heuristics; speed improvements; Circuits; Clustering algorithms; Computer science; Data mining; Design automation; Design optimization; Partitioning algorithms; Runtime; Software algorithms; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
  • Conference_Location
    Yokohama, Japan
  • Print_ISBN
    0-7803-5973-9
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2000.835182
  • Filename
    835182