Efficient reduction techniques for statistical model generation of standard cells

Statistical analysis has become an important technique to accurately factor in the effect of process variations in circuit behavior. Statistical analysis techniques depend on the generation of compact, fast, accurate and robust models that capture some specific aspect of the circuit behavior. The process of characterizing the circuit behavior to generate variation-aware models for standard cells has a large runtime penalty (l00x of nominal model generation). This runtime explosion is primarily due to the additional numbers of simulations required to capture the effects of within-die (WID) variations. We look at the techniques used for capturing WID effects in model generation and present some techniques to reduce the runtime of statistical delay and leakage characterization significantly. We show that our technique can speed up timing model generation by l0x and leakage model generation by approximately 2x.