Comparison of semiclassical transport formulations including quantum corrections for advanced devices with High-K gate stacks

Author

Bufler, F.M. ; Aubry-Fortuna, V. ; Bournel, A. ; Braccioli, M. ; Dollfus, P. ; Esseni, D. ; Fiegna, C. ; Gamiz, F. ; De Michielis, M. ; Palestri, P. ; Saint-Martin, J. ; Sampedro, C. ; Sangiorgi, E. ; Selmi, L. ; Toniutti, P.

Author_Institution

IIS, ETH Zurich, Zürich, Switzerland

fYear

2010

fDate

26-29 Oct. 2010

Firstpage

1

Lastpage

4

Abstract

Long-channel effective mobilities as well as transfer characteristics of a 32 nm single-gate SOI and a 16 nm double-gate (DG) MOSFET have been simulated with live different Monte Carlo (MC) device simulators. The differences are mostly rather small for the SOI-FET with quantum effects having a minor effect on threshold voltage due to the lowly doped channel, while the two multi-subband MC simulators show some prominent deviations in the case of the DG-FET. High-K mobility degradation by remote phonon scattering (RPS) in free carrier MC approximation leads to smaller performance degradation compared to multi-subband MC with remote Coulomb scattering (RCS) and RPS, but requires further investigations.

Keywords

MOSFET; Monte Carlo methods; field effect transistors; high-k dielectric thin films; silicon-on-insulator; Monte Carlo device simulator; RCS; RPS; SOI-FET; double-gate MOSFET; free carrier MC approximation; high-K gate stacks; quantum correction; quantum effect; remote Coulomb scattering; remote phonon scattering; semiclassical transport formulation; size 16 nm; size 32 nm; threshold voltage; Logic gates; MOSFET circuits; Monte Carlo methods; Phonons; Scattering; Silicon; Surface roughness;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Electronics (IWCE), 2010 14th International Workshop on

Conference_Location

Pisa

Print_ISBN

978-1-4244-9383-8

Type

conf

DOI

10.1109/IWCE.2010.5677952

Filename

5677952