DocumentCode :
1892107
Title :
Vertical Slit Field Effect Transistor in ultra-low power applications
Author :
Qiu, Xiang ; Marek-Sadowska, Malgorzata ; Maly, Wojciech
Author_Institution :
ECE Dept., Univ. of California, Santa Barbara, CA, USA
fYear :
2012
fDate :
19-21 March 2012
Firstpage :
384
Lastpage :
390
Abstract :
Vertical Slit Field Effect Transistors (VeSFETs) are novel twin-gate and junction-less devices with nearly ideal sub-threshold swing and manufactured using SOI infrastructure. In this paper, we analyze VeSFETs as potential components of ultra-low power circuits. We compare circuits built with VeSFETs, FinFETs, and bulk-MOSFETs, all in 65nm technology node. Our experiments demonstrate that VeSFET has the smallest intrinsic capacitance and the lowest minimum energy among the studied devices. The Tied-Gate (TG) VeSFET-based circuit operating at the minimum energy point achieves a lower energy and a higher frequency than its Independent-Gate (IG) VeSFET-based counterpart. IG VeSFET achieves lower energy for circuits working at extremely low and relatively wide frequency range.
Keywords :
MOSFET; capacitance; low-power electronics; silicon-on-insulator; FinFET; IG VeSFET; SOI infrastructure; bulk-MOSFET; independent-gate; intrinsic capacitance; junction-less device; size 65 nm; sub-threshold swing; technology node; tied-gate VeSFET-based circuit; twin-gate device; ultra-low power application; ultra-low power circuit; vertical slit field effect transistor; Capacitance; Energy efficiency; Integrated circuit modeling; Inverters; Logic gates; Ring oscillators; Switches; VeSFET; energy; performance; ring oscillator; subthreshold logic; subthreshold swing; twin-gate;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-4673-1034-5
Type :
conf
DOI :
10.1109/ISQED.2012.6187522
Filename :
6187522
Link To Document :
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