CMOS mixed signal fingerprint sensing and parallel processing architecture

Author

Seddeek, Faisal El ; Ismail, Mahmoud H. ; Aboudina, Mohamed M. ; Oussef, Mohamed A Y ; Soliman, Ahmed M.

Author_Institution

Fac. of Eng., Cairo Univ., Giza, Egypt

fYear

2002

fDate

2002

Firstpage

295

Lastpage

299

Abstract

A CMOS fingerprint sensing and parallel processing architecture is implemented on two chips. The first captures the fingerprint and transfers the pattern to the second. The sensors on the first chip are implemented based on a capacitive technique. The parallel processing algorithms include gap removal, spur removal, and thinning. In addition, a novel processing architecture has been implemented using vMOS transistors. Parallel operation of the processing units reduces power dissipation. Both chips use a standard CMOS process, with double poly layers and two metal layers.

Keywords

CMOS analogue integrated circuits; CMOS digital integrated circuits; capacitive sensors; fingerprint identification; image thinning; integrated circuit design; interference suppression; parallel processing; CMOS architecture; authentication; biometric systems; fingerprint sensor; gap removal; image processing; parallel processing; spur removal; thinning; vMOS transistors; Biosensors; CMOS process; Capacitance; Capacitive sensors; Circuits; Fingerprint recognition; Optical sensors; Parallel processing; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean

Print_ISBN

0-7803-7527-0

Type

conf

DOI

10.1109/MELECON.2002.1014577

Filename

1014577