Design and optimization of power gating for DVFS applications

Combined with dynamic voltage and frequency scaling (DVFS), power gating can be used effectively to improve the overall power efficiency of a chip design. Since the DVFS is applied to multiple supply voltage levels, the design tradeoffs between supply noise and power saving can vary significantly across different operating points. Hence, the tradeoffs have to be considered carefully by designers. In this paper, a systematic design tradeoff analysis for power gating geared towards DVFS applications is presented. We propose a multi-driver based scheme to drive sleep transistors. Re-routable decoupling capacitance based design strategies are used to balance supply noises and power saving at different supply levels. Finally, we demonstrate a simulation-based automatic design flow to improve the performance of power delivery network.