DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM

A system for layout exploration without design-rule checking is presented. It comprises of two key and new capabilities: 1) layout morphing to generate multi-mask layer layout variants, given basis layouts, and 2) feature-driven layout quality evaluation using through-process patterning simulations. The former uses morphing techniques inspired from image processing. The latter uses design-specific marker shapes to identify relevant features and efficient geometric operations on the simulated contours and these markers. The methodology is useful for high-density layout design and design rule development where design rules are insufficient or irrelevant, especially at 22 nm technology and beyond. We demonstrate it on an aggressive 22 nm SRAM bitcell design.