DocumentCode :
1892567
Title :
VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS
Author :
Samandari-Rad, Jeren ; Guthaus, Matthew ; Hughey, Richard
Author_Institution :
Dept. of Electr. Eng., UCSC, Santa Cruz, CA, USA
fYear :
2012
fDate :
19-21 March 2012
Firstpage :
506
Lastpage :
515
Abstract :
In this paper we propose a new hybrid analytical-empirical model, called VAR-TX, that exhaustively computes and compares all feasible architectures subject to inter-die (DID) and intra-die (WID) process variations (PV). Based on its computation, VAR-TX predicts the optimal architecture that provides minimum access-time and minimum access-time variation for yield enhancement in future 16-nm on-chip conventional six-transistor static random access memories (6T-SRAMs) of given input specifications. These specifications include SRAM size and shape, number of columns, and word-size. We compare the impact of D2D and WID variations on access-time for 16-nm SRAM with the 45-nm and 180-nm nodes and demonstrate that the drastic increase in the 1- and 3-sigma of the smaller nodes is mainly due to the increase in the WID variations. Finally, our model disputes previously published works-suggesting that square SRAM always produces minimum delays-and significantly extends and enhances the older models by adding both an extra dimension of architectural consideration and additional device parameter fluctuation to the analysis, while producing delay estimates within 4% of Hspice results.
Keywords :
CMOS memory circuits; SRAM chips; delay estimation; D2D PV; VAR-TX; WID PV; delay estimation; device parameter fluctuation; hybrid analytical-empirical model; interdie process variation; intradie process variation; minimum access-time achievement; nanoscaled CMOS techonology; on-chip conventional 6T-SRAM; on-chip conventional six-transistor static random access memories; optimum architecture; size 16 nm; size 180 nm; size 45 nm; variability-aware SRAM model; yield enhancement; Analytical models; Computer architecture; Delay; Logic gates; Random access memory; Sensitivity; Transistors; SRAM; access-time; optimum architecture; variability; yield;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-4673-1034-5
Type :
conf
DOI :
10.1109/ISQED.2012.6187541
Filename :
6187541
Link To Document :
بازگشت