DocumentCode
1892601
Title
The design and implementation of double-precision multiplier in a first-generation CELL processor
Author
Kuang, J.B. ; Buchholtz, T.C. ; Dance, S.M. ; Warnock, J.D. ; Storino, S.N. ; Wendel, D. ; Bradley, D.H.
Author_Institution
Austin Res. Lab., IBM, Austin, TX, USA
fYear
2005
fDate
9-11 May 2005
Firstpage
11
Lastpage
14
Abstract
We present the double precision multiplier for a 90nm PD-SOI first-generation CELL processor. Dynamic booth logic is designed for scalability and with noise, leakage, and pulse width variation tolerance. Static partial product compression is implemented with replicated bits for performance. The design supports fine-grained clock gating domains for active power reduction.
Keywords
clocks; logic design; microprocessor chips; multiplying circuits; silicon-on-insulator; 90 nm; PD-SOI; active power reduction; double-precision multiplier; dynamic booth logic; fine-grained clock gating; first-generation CELL processor; replicated bits; static partial product compression; Circuits; Clocks; Delay; Laboratories; Latches; Logic design; Scalability; Space vector pulse width modulation; Streaming media; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN
0-7803-9081-4
Type
conf
DOI
10.1109/ICICDT.2005.1502577
Filename
1502577
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