Design aspects of a microprocessor data cache using 3D die interconnect technology

This paper explores an implementation of a new technology called 3D die stacking. 3D die stacking is the bonding of two die either face-to-face or face-to-back in order to construct a 3D structure. In this work a face-to-face bonding is utilized because it yields a higher density die-to-die interconnect than is possible with face-to-back. With sufficiently dense die-to-die interconnect, devices as complex as an iA32 microprocessor can be repartitioned or split between two die in order to simultaneously improve performance and power. The 3D structure of this emerging technology is examined and applied in this paper to a conventional 2D 32KB data cache. In this study, it is shown that a 3D implementation can potentially improve the silicon area, complexity, performance and power of a 2D circuit simultaneously.