DocumentCode
1892672
Title
A scalable stepped gate sensing scheme for sub-100nm multilevel flash memory
Author
Bauer, M. ; Tedrow, K.
Author_Institution
Intel Corp., Folsom, CA, USA
fYear
2005
fDate
9-11 May 2005
Firstpage
23
Lastpage
26
Abstract
As flash memory cell size scales with lithography, the storage capacitance area scales resulting in the need to sense fewer electrons that are stored on a floating gate. A stepped-gate sensing scheme for NOR flash memories with multilevel storage are presented. Stepped-gate sensing motivation, scalability advantages and implementation are discussed.
Keywords
NOR circuits; flash memories; memory architecture; 100 nm; NOR flash memories; floating gate; lithography; multilevel flash memory; multilevel storage; scalable stepped gate sensing; storage capacitance area; Capacitance; Circuit synthesis; Electrons; Flash memory; Flash memory cells; Integrated circuit interconnections; Lithography; Nonvolatile memory; Scalability; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN
0-7803-9081-4
Type
conf
DOI
10.1109/ICICDT.2005.1502580
Filename
1502580
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