Design and development of 130nm ICs for a 720 Gb/s networking system

Author

Khan, Ajmal ; Ruparel, K. ; Joly, C. ; Ghanta, V. ; Le, Dat ; Nguyen, Thin ; Yang, Songping ; Ahmed, Ishtiaq ; Burnside, N. ; Cheung, Man Hon ; Chiu, F. ; Fan, Y. ; Ge, Dasong ; Gill, Jaswinder ; Huang, Pei-Yu ; Jayapal, V. ; Kim, Oleksiy ; Li, Meng ; Ngu

Author_Institution

Cadence Design Syst., Inc., San Jose, CA, USA

fYear

2005

fDate

9-11 May 2005

Firstpage

53

Lastpage

56

Abstract

A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. ∼76M transistors are integrated in a 130nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.

Keywords

CMOS integrated circuits; integrated circuit design; switching networks; system-on-chip; 130 nm; 720 Gbit/s; CMOS process; design validation; electrical design method; multigigabit switching network system; networking IC design; physical design method; power distribution; signal integrity; Buffer storage; CMOS process; Control systems; Design methodology; Engines; Packaging; Packet switching; Random access memory; Signal design; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Print_ISBN

0-7803-9081-4

Type

conf

DOI

10.1109/ICICDT.2005.1502589

Filename

1502589