24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits

A post-fabrication dual supply voltage (V_DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V_DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V_DD below V_DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC´S circuit fabricated in 65nm CMOS. The layout of DES CODEC´S is divided into 64 V_DD domains and each domain size is 54μm × 63.2μm. High V_DD (V_DDH) or low V_DD (V_DDL) is applied to each domain and the selection of V_DD´s is performed based on multiple built-in self tests. V_DDH is selected in V_DDmin-critical domains, while V_DDL is selected in V_DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V_DDH = 3D437mV, and V_DDL = 3D397mV.