Title :
Challenges in implementing high-k dielectrics in the 45nm technology node
Author :
Lee, B.H. ; Song, S.C. ; Choi, R. ; Wen, H.-C. ; Majhi, P. ; Kirsch, P. ; Young, C. ; Ersuker, G.
Author_Institution :
SEMATECH, Austin, TX, USA
Abstract :
Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.
Keywords :
CMOS integrated circuits; dielectric materials; 45 nm; CMOS device; high-k dielectrics; high-k gate stack technology; metal gate stack technology; CMOS technology; Degradation; Electrodes; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Leakage current; MOSFETs; Optical scattering; Phonons;
Conference_Titel :
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN :
0-7803-9081-4
DOI :
10.1109/ICICDT.2005.1502595
