Two-dimensional borderless contact pad technology for a 0.135 /spl mu/m/sup 2/ 4-gigabit DRAM cell

Author

Koga, H. ; Matsuki, T. ; Kasai, N. ; Tatsumi, T. ; Hayashi, Y. ; Saito, Y. ; Nakajima, K. ; Tokunaga, K. ; Yamada, Y. ; Onoda, N. ; Tokashiki, K. ; Nishizawa, A. ; Kawamoto, H. ; Koyama, K.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

25

Lastpage

28

Abstract

We have developed a contact pad structure made by using a Ge-added anisotropic selective epitaxial Si growth technique and Si/sub 3/N/sub 4/ CMP technique. This contact structure has a large alignment tolerance not only for the word line but also for the isolation. We have used this structure to make a 0.135-/spl mu/m/sup 2/ folded-bit-line memory cell for a 4-gigabit DRAM with a 0.12-/spl mu/m design rule and have obtained 0.07-/spl mu/m alignment tolerance for both the word line and the isolation.

Keywords

DRAM chips; epitaxial growth; integrated circuit layout; integrated circuit metallisation; isolation technology; polishing; semiconductor growth; 0.12 micron; 2D borderless contact pad technology; 4 Gbit; Ge-added epitaxial Si growth; Si; Si/sub 3/N/sub 4/; Si/sub 3/N/sub 4/ CMP technique; alignment tolerance; anisotropic selective epitaxial growth technique; chemical-mechanical polishing; dynamic RAM; folded-bit-line memory cell; gigabit DRAM cell; isolation; self-aligned contact structure; word line; Anisotropic magnetoresistance; Atherosclerosis; Dielectric films; Etching; Laboratories; National electric code; Random access memory; Semiconductor films; Silicon; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.649444

Filename

649444