Transformational-based synthesis of VLSI based DSP systems for low power using a genetic algorithm

This paper describes a technique for the synthesis of CMOS based DSP systems under multiple design constraints. The primary target of the technique is to reduce operating power by applying high level transformations to designs. During the search for a low power solution the technique considers issues at circuit and layout levels, using appropriate capacitive models, together with tracking speed and area design constraints. In exploring the complex search space of the synthesis problem the technique uses a genetic algorithm which utilises a library of high level transformation based techniques within its operators. The paper describes the technique, the capacitive models used for power estimation and presents results for DSP systems of varying complexity. The results demonstrate the significant power savings achieved with the technique