Title :
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices
Author :
Yang, Kaiyuan ; Kim, Dae Hyun ; Lim, Sung Kyu
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller footprint area, shorter wire-length, and better performance than 2D ICs. However, the quality of 3D ICs is strongly dependent on TSV dimensions and parasitics. Using large TSVs may cause silicon area overhead and reduce the amount of wirelength reduction in 3D ICs. In addition, non-negligible TSV parasitic capacitance can result in delay overhead affecting the delay of 3D ICs. Meanwhile, with the development of TSV manufacturing technology, nano-scale TSVs are emerging, which is expected to reduce the overheads caused by using large TSVs. Therefore, this paper investigates the impact of nano-scale TSVs on the quality of 3D ICs at future technology nodes. For this study, we develop a 16nm standard cell library, design 3D ICs using different process technologies (45nm, 22nm, and 16nm) and various TSVs diameters (from 5μm to 0.1μm), and discuss the impact of nano-scale TSVs.
Keywords :
integrated circuit design; three-dimensional integrated circuits; 2D IC; 3D IC; TSV manufacturing technology; design quality tradeoff studies; footprint area; nanoscale TSV; nanoscale devices; nonnegligible parasitic capacitance; process technologies; size 16 nm; size 22 nm; size 45 nm; size 5 mum to 0.1 mum; standard cell library; three dimensional integrated circuits; through-silicon vias dimensions; wirelength reduction; Delay; Inverters; Libraries; Logic gates; Metals; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-1034-5
DOI :
10.1109/ISQED.2012.6187574
