STG optimization for power and area reduction

Graph transformations for deterministic Signal Transition Graphs (STGs) are presented. The proposed transformations can result in more efficient circuits with respect to power consumption and area, by reducing the STG signals concurrency, provided that the timing restrictions of the circuit are not violated. The circuits´ function and speed are preserved. The proposed graph modifications steps are presented in a procedural, clearly defined algorithm. So the transformations can be very easily integrated in existed STG synthesis tools