Title :
STG optimization for power and area reduction
Author :
Panagiotaras, G.S. ; Koufopavlou, O.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
fDate :
31 May-3 Jun 1998
Abstract :
Graph transformations for deterministic Signal Transition Graphs (STGs) are presented. The proposed transformations can result in more efficient circuits with respect to power consumption and area, by reducing the STG signals concurrency, provided that the timing restrictions of the circuit are not violated. The circuits´ function and speed are preserved. The proposed graph modifications steps are presented in a procedural, clearly defined algorithm. So the transformations can be very easily integrated in existed STG synthesis tools
Keywords :
circuit optimisation; logic design; signal flow graphs; STG optimization; algorithm; area; circuit synthesis; deterministic signal transition graph; graph transformation; power consumption; Asynchronous circuits; Circuit synthesis; Concurrent computing; Design engineering; Energy consumption; Laboratories; Power engineering computing; Signal design; Signal synthesis; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705212
